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arch: arm: Fix incorrect Cortex-R interrupt state control logic. #20474
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andrewboie
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arch: arm: Fix incorrect Cortex-R interrupt state control logic. #20474
andrewboie
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zephyrproject-rtos:master
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stephanosio:cortex_r_fix_irq_mgmt
Feb 11, 2020
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This commit fixes incorrect Cortex-R interrupt lock, unlock and state check function implementations. The issues can be summarised as follows: 1. The current implementation of 'z_arch_irq_lock' returns the value of CPSR as the IRQ key and, since CPSR contains many other state bits, this caused 'z_arch_irq_unlocked' to return false even when IRQ is unlocked. This problem is fixed by isolating only the I-bit of CPSR and returning this value as the IRQ key, such that it returns a non-zero value when interrupt is disabled. 2. The current implementation of 'z_arch_irq_unlock' directly updates the value of CPSR control field with the IRQ key and this can cause other state bits in CPSR to be corrupted. This problem is fixed by conditionally enabling interrupt using CPSIE instruction when the value of IRQ key is a zero. 3. The current implementation of 'z_arch_is_in_isr' checks the value of CPSR MODE field and returns true if its value is IRQ or FIQ. While this does not normally cause an issue, the function can return false when IRQ offloading is used because the offload function executes in SVC mode. This problem is fixed by adding check for SVC mode. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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This commit introduces the common tick margin definition that can be used to specify the maximum allowable deviation from the expected number of ticks. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Xilinx QEMU, used to emulate the Xilinx ZynqMP platform, is particularly unstable in terms of timing. This commit increases the tick margin for the Xilinx ZynqMP platform from 1 to 5 in order to allow the sleep test to pass with a reasonable repeatability. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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This commit removes the ignore tags for the tests that work after the changes in the PR zephyrproject-rtos#22037. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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area: API
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area: ARM
ARM (32-bit) Architecture
area: Boards
area: Kernel
area: Tests
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This commit fixes incorrect Cortex-R interrupt lock, unlock and state
check function implementations.
The issues can be summarised as follows:
The current implementation of 'z_arch_irq_lock' returns the value
of CPSR as the IRQ key and, since CPSR contains many other state
bits, this caused 'z_arch_irq_unlocked' to return false even when
IRQ is unlocked. This problem is fixed by isolating only the I-bit
of CPSR and returning this value as the IRQ key, such that it
returns a non-zero value when interrupt is disabled.
The current implementation of 'z_arch_irq_unlock' directly updates
the value of CPSR control field with the IRQ key and this can cause
other state bits in CPSR to be corrupted. This problem is fixed by
conditionally enabling interrupt using CPSIE instruction when the
value of IRQ key is a zero.
The current implementation of 'z_arch_is_in_isr' checks the value
of CPSR MODE field and returns true if its value is IRQ or FIQ.
While this does not normally cause an issue, the function can return
false when IRQ offloading is used because the offload function
executes in SVC mode. This problem is fixed by adding check for SVC
mode.
Signed-off-by: Stephanos Ioannidis root@stephanos.io
NOTE: